The invention relates to CMOS integrated circuits and particularly to fast optional signal inversion or polarity control.
In this description, equivalent elements are given the same reference numbers throughout the figures and are not described more than once.
In programmable logic devices, it is often useful to offer optional inversion of a signal so that a user may invert the polarity of the signal but only when desired. FIG. 1 shows a well known circuit for applying both inverted and non-inverted versions of an input signal IN to a multiplexer M. A select signal SEL determines whether the multiplexer will provide the inverted or non-inverted input signal as the output signal OUT.
FIG. 2 shows one implementation of this circuit. Inverter 1 causes the inverted signal to arrive at multiplexer M at a later time than does the non-inverted signal. Also, inverter 2 causes the non-inverted signal path through transistor 4 to switch at a later time than does the inverted signal path through transistor 3. As the speed of signals increases, the fact that the inverted and non-inverted signals arrive at multiplexer M at different times becomes significant.
In order to increase internal operating speed, circuit designers sometimes use clock frequency doublers such as shown in FIG. 3. These circuits cause pulses to be generated on both rising and falling edges of the input signal. The circuit of FIG. 3 provides a low output signal whenever the input signal has been in a steady state long enough that the input signal IN has propagated through inverters 31, 32, and 33 to NAND gate 34 and NOR gate 35 so that both NAND gate 34 and NOR gate 35 receive differing versions of input signal IN. Thus NAND gate 34 outputs a high steady state signal and NOR gate 35 outputs a low steady state output signal. Since inverter 36 inverts the NOR gate signal again, both inputs to NAND gate 37 in this steady state are high, and NAND gate 37 outputs a low signal. But when input signal IN switches from low to high, both inputs to NAND gate 34 go temporarily high, so NAND gate 34 outputs a low signal, causing NAND gate 37 to output a high OUT signal until the signal propagates through inverters 31, 32, and 33 and NAND gate 34 again goes high. Similarly, when input signal IN switches from high to low, there is a period of time when the lower input to NOR gate 35 has gone low and the upper input to NOR gate 35 is still low, so that NOR gate 35 outputs a high signal, causing inverter 36 to provide a low signal to NAND gate 37, thus causing NAND gate 37 to output a high OUT signal until the switching of inverters 31-33 has propagated and caused NAND gate 37 to again go low.
FIG. 4 shows the pulses in output signal OUT that occur on every transition of input clock signal IN, and illustrates that output signal OUT transitions twice as often as input signal IN.
Circuit designers sometimes want both the clock doubling function and the polarity select function. FIG. 5 shows a 3-to-1 multiplexer circuit M5 that combines the polarity select function of FIG. 1 with the clock doubler function of FIG. 3. In order to save power, pass transistor 6 is placed at the input of the clock doubler circuit. To isolate the clock doubler circuit when not in use, transistor 7 is placed at the output. To prevent floating of the input to inverter 31 when transistor 6 is off, a P-channel transistor 52 is provided, and in order to prevent transistors in inverter 31 from forming a conductive path in response to an intermediate input signal, a P-channel pull-up transistor 51 is provided to pull the input of inverter 31 all the way to Vcc when input signal IN is high. P-channel half-latch transistor 5 is optionally provided if needed to prevent the input of inverter 1 from remaining at an intermediate voltage. Three select signals SEL1, SEL2, and SEL3 are provided to control transistors 3, 4, and 7 respectively, and only one select signal is brought high to enable one of the paths through multiplexer M5.
However, the delay through the clock doubler circuit plus transistors 6 and 7 causes the circuit of FIG. 5 to be undesirably slow. The path that first produces low-to-high switching of output signal OUT is through transistor 6, NAND gate 34, NAND gate 37, and pass transistor 7. High-to-low switching requires the signal to propagate through transistor 6, NOR gate 35, inverter 36, NAND gate 37, and pass transistor 7, or a total of five devices. It would be desirable to offer the clock doubling function in combination with the polarity select function without incurring the kind of delay resulting from the circuit of FIG. 5.
In one embodiment, the invention achieves high speed switching between inverted and non-inverted paths from an input terminal to an output terminal by placing a CMOS inverter in the inverted path, and using a path selector that drives the two power terminals of the CMOS inverter as well as controlling the non-inverted path. When the path selector is in one state, the CMOS inverter is powered that it does not conduct a signal from input to output and the non-inverted path (a pass gate or a transmission gate) does conduct. When the path selector is in the other state, the CMOS inverter inverts the input signal to generate an output signal and the non-inverting path does not conduct.
In another embodiment, a clock doubling pulse generator is achieved by using a delay circuit for selecting between inverting and non-inverting paths, the delay circuit receiving the input signal, and responding to the input signal by switching state a period of time after the input signal has switched state. Since the delay circuit controls whether the signal is inverted or not, the state of the output signal changes quickly in response to a change in the input signal and then the output signal returns to its former state after the delay has passed. Thus the output signal switches state on every high and every low transition of the input signal, effectively doubling the switching frequency of the input signal.
According to another aspect of the invention, the polarity of the output signal with respect to the input signal is selectable. A pair of inverted and non-inverted paths provide an output signal in response to an input signal. As a clock-doubling feature of the invention, selection of one of the paths is made by a delay circuit that receives the input signal and changes the selection after a delay has passed.
The inverting and non-inverting paths may both be transmission gates. Or the non-inverting path may be a transmission gate and the inverting path may be a CMOS inverter with the sources of the P-channel and N-channel transistors driven by a select signal and its inverse. The select signal may be an independent polarity control signal or a delayed version of the input signal to achieve clock doubling.
The invention achieves very fast switching in response to an input signal and can therefore respond to higher frequency clock signals than can prior art circuits.